module MUTEX(input bit [1:0] in, output bit [1:0] out); always @* casez ({int'(in), int'(out)}) {0, 'z}: out = 0; {1, 'z}: out = 1; {2, 'z}: out = 2; {3, 1}: out = 1; {3, 2}: out = 2; {3, 0}: out = 1; // in[0] wins {3, 3}: out = 1; // in[0] wins, I said! endcase endmodule
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