vak: (Default)
Serge Vakulenko ([personal profile] vak) wrote 2019-04-05 05:15 am (UTC)

У VHDL есть один неоспоримый плюс: можно купить _одну_ книжку и выучить весь язык. С SystemVerilog так не получится. Нужно как минимум три книжки, да еще в стандарт заглядывать.
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