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Берём Yosys: бесплатный открытый софт для синтеза. Его можно легко собрать из исходников под Линукс, или скачать готовый для RedHat или Windows. В качестве примера создаём файл example.v на языке Verilog:
Понадобится также скрипт с директивами для Yosys:
Запускаем:
Откроется окошко с получившейся схемой:

На схеме можно видеть сумматор, мультиплексор и D-триггер.
Подробности можно прочитать в статье "Yosys Application Note 011: Interactive Design Investigation".
module example(input clk, a, b, c, output reg [1:0] y); always @(posedge clk) if (c) y <= a + b; endmodule
Понадобится также скрипт с директивами для Yosys:
read_verilog example.v proc opt show -pause
Запускаем:
$ yosys example.ys /----------------------------------------------------------------------------\ | | | yosys -- Yosys Open SYnthesis Suite | | | | Copyright (C) 2012 - 2016 Clifford Wolf | | | | Permission to use, copy, modify, and/or distribute this software for any | | purpose with or without fee is hereby granted, provided that the above | | copyright notice and this permission notice appear in all copies. | | | | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | | | \----------------------------------------------------------------------------/ Yosys 0.6+152 (git sha1 b5a9fba, gcc 5.4.0-6ubuntu1~16.04.1 -fPIC -Os) -- Executing script file `example.ys' -- 1. Executing Verilog-2005 frontend. Parsing Verilog input from `example.v' to AST representation. Generating RTLIL representation for module `\example'. Successfully finished Verilog frontend. 2. Executing PROC pass (convert processes to netlists). 2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Cleaned up 0 empty switches. 2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Removed a total of 0 dead cases. 2.3. Executing PROC_INIT pass (extract init attributes). 2.4. Executing PROC_ARST pass (detect async resets in processes). 2.5. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `\example.$proc$example.v:4$1'. 1/1: $0\y[1:0] 2.6. Executing PROC_DLATCH pass (convert process syncs to latches). 2.7. Executing PROC_DFF pass (convert process syncs to FFs). Creating register for signal `\example.\y' using process `\example.$proc$example.v:4$1'. created $dff cell `$procdff$6' with positive edge clock. 2.8. Executing PROC_CLEAN pass (remove empty switches from decision trees). Found and cleaned up 1 empty switch in `\example.$proc$example.v:4$1'. Removing empty process `example.$proc$example.v:4$1'. Cleaned up 1 empty switch. 3. Executing OPT pass (performing simple optimizations). 3.1. Executing OPT_EXPR pass (perform const folding). 3.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\example'. Removed a total of 0 cells. 3.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \example.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Root of a mux tree: $procmux$4 (pure) Analyzing evaluation results. Removed 0 multiplexer ports. 3.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \example. Performed a total of 0 changes. 3.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\example'. Removed a total of 0 cells. 3.6. Executing OPT_RMDFF pass (remove dff with constant values). Replaced 0 DFF cells. 3.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \example.. 3.8. Executing OPT_EXPR pass (perform const folding). 3.9. Finished OPT passes. (There is nothing left to do.) 4. Generating Graphviz representation of design. Writing dot description to `/home/vak/.yosys_show.dot'. Dumping module example to page 1. Exec: { test -f '/home/vak/.yosys_show.dot.pid' && fuser -s '/home/vak/.yosys_show.dot.pid'; } || ( echo $$ >&3; exec xdot '/home/vak/.yosys_show.dot'; ) 3> '/home/vak/.yosys_show.dot.pid' & Press ENTER to continue (or type 'shell' to open a shell)> _
Откроется окошко с получившейся схемой:

На схеме можно видеть сумматор, мультиплексор и D-триггер.
Подробности можно прочитать в статье "Yosys Application Note 011: Interactive Design Investigation".