Тестируем парсер асинхронного диалекта Verilog

[vak]

В качестве теста возьмём упомянутый наибольший делитель.

module gcd (
    input        activate,
    input  [7:0] a,
    input  [7:0] b,
    output [7:0] c
);
    reg [7:0] x, y;

    always while (activate) begin
        fork
            x <= a;
            y <= b;
        join

        while select
        x > y:
            x = x - y;
        y > x:
            y = y - x;
        endselect

        c <= x;
    end
endmodule

Парсер преобразует исходный текст в следующее синтаксическое дерево:

DESIGN
| MODULE 'gcd' <2:8>
| | WIRE 'activate' <3:18> input port=1
| | WIRE 'a' <4:18> input port=2
| | | RANGE <4:12>
| | | | CONSTANT 7 <4:13> signed range=[31:0] bits32=00000000000000000000000000000111
| | | | CONSTANT 0 <4:15> signed range=[31:0] bits32=00000000000000000000000000000000
| | WIRE 'b' <5:18> input port=3
| | | RANGE <5:12>
| | | | CONSTANT 7 <5:13> signed range=[31:0] bits32=00000000000000000000000000000111
| | | | CONSTANT 0 <5:15> signed range=[31:0] bits32=00000000000000000000000000000000
| | WIRE 'c' <6:18> output port=4
| | | RANGE <6:12>
| | | | CONSTANT 7 <6:13> signed range=[31:0] bits32=00000000000000000000000000000111
| | | | CONSTANT 0 <6:15> signed range=[31:0] bits32=00000000000000000000000000000000
| | WIRE 'x' <8:15> reg
| | | RANGE <8:9>
| | | | CONSTANT 7 <8:10> signed range=[31:0] bits32=00000000000000000000000000000111
| | | | CONSTANT 0 <8:12> signed range=[31:0] bits32=00000000000000000000000000000000
| | WIRE 'y' <8:18> reg
| | | RANGE <8:9>
| | | | CONSTANT 7 <8:10> signed range=[31:0] bits32=00000000000000000000000000000111
| | | | CONSTANT 0 <8:12> signed range=[31:0] bits32=00000000000000000000000000000000
| | ALWAYS <10:5>
| | | BLOCK <10:5>
| | | | WHILE <10:12>
| | | | | IDENTIFIER 'activate' <10:19>
| | | | | BLOCK <10:27>
| | | | | | BLOCK <10:29>
| | | | | | | PARBLOCK <11:9>
| | | | | | | | ASSIGN_LE <12:15>
| | | | | | | | | IDENTIFIER 'x' <12:13>
| | | | | | | | | IDENTIFIER 'a' <12:18>
| | | | | | | | ASSIGN_LE <13:15>
| | | | | | | | | IDENTIFIER 'y' <13:13>
| | | | | | | | | IDENTIFIER 'b' <13:18>
| | | | | | | SELECTLOOP <16:9>
| | | | | | | | COND <17:11>
| | | | | | | | | GT <17:11>
| | | | | | | | | | IDENTIFIER 'x' <17:9>
| | | | | | | | | | IDENTIFIER 'y' <17:13>
| | | | | | | | | BLOCK <17:11>
| | | | | | | | | | ASSIGN_EQ <18:15>
| | | | | | | | | | | IDENTIFIER 'x' <18:13>
| | | | | | | | | | | SUB <18:19>
| | | | | | | | | | | | IDENTIFIER 'x' <18:17>
| | | | | | | | | | | | IDENTIFIER 'y' <18:21>
| | | | | | | | COND <19:11>
| | | | | | | | | GT <19:11>
| | | | | | | | | | IDENTIFIER 'y' <19:9>
| | | | | | | | | | IDENTIFIER 'x' <19:13>
| | | | | | | | | BLOCK <19:11>
| | | | | | | | | | ASSIGN_EQ <20:15>
| | | | | | | | | | | IDENTIFIER 'y' <20:13>
| | | | | | | | | | | SUB <20:19>
| | | | | | | | | | | | IDENTIFIER 'y' <20:17>
| | | | | | | | | | | | IDENTIFIER 'x' <20:21>
| | | | | | | ASSIGN_LE <23:11>
| | | | | | | | IDENTIFIER 'c' <23:9>
| | | | | | | | IDENTIFIER 'x' <23:14>

Осталось научиться генерить из этого дерева асинхронную схему.