x86-S

[vak]

Встречайте новую интеловскую архитектуру.

Intel proposes the x86-S architecture for a simpler, more efficient CPU instruction set

X86-S External Architectural Specification Rev.1.0 (PDF)

X86-S is a legacy-reduced-OS ISA that removes outdated execution modes and operating system ISA.

The presence of the X86-S ISA is enumerated by a single, main CPUID feature bit LEGACY_REDUCED_OS_ISA in a future CPUID field. The bit implies all the ISA removals described in this document. Some of the additional features, like 64bit SIPI or the 5 Level page table switch, have separate CPUID feature flags and can be implemented independently of X86-S.

Changes in X86-S ISA consist of:

• restricting the CPU to be always in paged mode
• removing 32-bit ring 0, as well as vm86 mode.
• removing ring 1 and ring 2
• removing 16-bit real and protected modes
• removing 16-bit addressing
• removing fixed MTRRs
• removing user-level I/O and string I/O
• removing CR0 Write-Through mode
• removing legacy FPU control bits in CR0
• removing ring 3 interrupt flag control
• removing obsolete CR access instruction
• rearchitecting INIT/SIPI
• adding a new mechanism to switch between 4- and 5-level page tables
• removing XAPIC and only supporting x2APIC
• removing APIC support for 8529
• removing the disabling of NX or SYSCALL or long mode in the EFER MSR
• removing the #SS and #NP exceptions
• supporting a subset of segmentation architecture, with the following conditions:
  • restricted to a subset of IDT event delivery
  • base only for FS, GS
  • base and limit for GDT, IDT, and TSS
  • no limit on data or code fetches in 32-bit mode (similar to 64-bit)
  • no AR or unusable selector checking on CS, DS, ES, FS, and GS on data or code
  • fetches in any mode
  • restricted support for far call, far return, far jump, and IRET (like FRED).