Простой пример на Verilog

[vak]

Собственно пост будет из трех частей.  Здесь часть первая, как бы предисловие.
Моделируем простейшую цифровую систему, состоящую из генератора частоты и 4-битного счетчика.
Текст на Верилоге:

`timescale 1ns / 1ns

module main;

    reg       clock;    /* Clock input of the design */
    reg       reset;    /* Active high, synchronous Reset */
    reg       enable;   /* Active high enable signal for counter */
    reg [3:0] count;    /* 4-bit counter */

    always begin
        clock <= 0;
        #10;
        clock <= 1;
        #10;
    end

    always @(posedge clock) begin
        if (reset)
            count <= 0;

        else if (enable) begin
            $display("(%0d) Incremented Counter %d", $time, count);
            count <= count + 1;
        end
    end

    initial begin
        #100;
        reset <= 1;
        $display ("(%0d) Asserting Reset", $time);

        #200;
        reset <= 0;
        $display ("(%0d) De-Asserting Reset", $time);

        #100;
        $display ("(%0d) Asserting Enable", $time);
        enable <= 1;

        #400;
        $display ("(%0d) De-Asserting Enable", $time);
        enable <= 0;

        $display ("(%0d) Terminating simulation", $time);
        $finish;
    end
endmodule

Запускаем в Линуксе. Предварительно надо установить симулятор Icarus Verilog. Итак:

$ iverilog -o example example.v
$ ./example 
(100) Asserting Reset
(300) De-Asserting Reset
(400) Asserting Enable
(410) Incremented Counter  0
(430) Incremented Counter  1
(450) Incremented Counter  2
(470) Incremented Counter  3
(490) Incremented Counter  4
(510) Incremented Counter  5
(530) Incremented Counter  6
(550) Incremented Counter  7
(570) Incremented Counter  8
(590) Incremented Counter  9
(610) Incremented Counter 10
(630) Incremented Counter 11
(650) Incremented Counter 12
(670) Incremented Counter 13
(690) Incremented Counter 14
(710) Incremented Counter 15
(730) Incremented Counter  0
(750) Incremented Counter  1
(770) Incremented Counter  2
(790) Incremented Counter  3
(800) De-Asserting Enable
(800) Terminating simulation
$ _