Тот же пример на Си
2013-02-25 13:28![[personal profile]](https://www.dreamwidth.org/img/silk/identity/user.png)
Часть вторая: то же самое, но без Верилога.
Подробности будут в третьей части. Текст на Си:
Подробности будут в третьей части. Текст на Си:
#include <stdio.h> #include "rtlsim.h" signal_t clock = signal_init ("clock", 0); /* Main clock of the design */ signal_t reset = signal_init ("reset", 0); /* Active high, synchronous Reset */ signal_t enable = signal_init ("enable", 0); /* Active high enable signal for counter */ signal_t count = signal_init ("count", 0); /* 4-bit counter */ void do_clock () { for (;;) { signal_set (&clock, 0); process_delay (10); signal_set (&clock, 1); process_delay (10); } } void do_counter () { /* Make a sensitivity list. */ process_sensitive (&clock, POSEDGE); for (;;) { /* Wait for event from the sensitivity list. */ process_wait(); /* At every rising edge of clock we check if reset is active. * If active, we load the counter output with 4'b0000. */ if (reset.value != 0) { signal_set (&count, 0); /* If enable is active, then we increment the counter. */ } else if (enable.value != 0) { printf ("(%llu) Incremented Counter %llu\n", time_ticks, count.value); signal_set (&count, (count.value + 1) & 15); } } } int main (int argc, char **argv) { /* Create processes with 4kbyte stacks. */ process_init ("clock", do_clock, 4096); process_init ("counter", do_counter, 4096); process_delay (100); signal_set (&reset, 1); printf ("(%llu) Asserting Reset\n", time_ticks); process_delay (200); signal_set (&reset, 0); printf ("(%llu) De-Asserting Reset\n", time_ticks); process_delay (100); printf ("(%llu) Asserting Enable\n", time_ticks); signal_set (&enable, 1); process_delay (400); printf ("(%llu) De-Asserting Enable\n", time_ticks); signal_set (&enable, 0); printf ("(%llu) Terminating simulation\n", time_ticks); return 0; }Запускаем:
$ make cc -c -o example.o example.c cc -c -o rtlsim.o rtlsim.c cc -o example example.o rtlsim.o $ ./example (100) Asserting Reset (300) De-Asserting Reset (400) Asserting Enable (410) Incremented Counter 0 (430) Incremented Counter 1 (450) Incremented Counter 2 (470) Incremented Counter 3 (490) Incremented Counter 4 (510) Incremented Counter 5 (530) Incremented Counter 6 (550) Incremented Counter 7 (570) Incremented Counter 8 (590) Incremented Counter 9 (610) Incremented Counter 10 (630) Incremented Counter 11 (650) Incremented Counter 12 (670) Incremented Counter 13 (690) Incremented Counter 14 (710) Incremented Counter 15 (730) Incremented Counter 0 (750) Incremented Counter 1 (770) Incremented Counter 2 (790) Incremented Counter 3 (800) De-Asserting Enable (800) Terminating simulation $ _