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vakНадыбал исходные коды микропрограммной реализации процессора ZPU: github.com/sergev/zpu-avalanche
Надо прикинуть, сложно ли будет переделать его на 24-битный размер команды и 48-битное слово.
"The ZPU is a very small, 32-bit processor, advertised by the developer Zylin as “the worlds smallest 32-bit CPU with GCC toolchain” [14]. The hardware description is licensed under a FreeBSD license and the software under the GNU General Public License (GPL). Both license models offer free redistribution and adaption of the sources, which is a prerequisite for modifications of the design.
The architecture of one ZPU Core is shown in Figure 2. It consists of only three main components: 1. The control and execution unit Execute does the instruction execution and address calculation; 2. The instruction decoder Decode x4 which fetches up to four instructions for decoding; 3. The stack registers Stack A and Stack B where two words from the main memory (Memory) stack are temporarily stored. The ZPU is a stack-based architecture; apart from Stack A and Stack B the ZPU has no further registers. Every calculation is done by first fetching the appropriate words sequentially from the stack to the registers and then executing the instruction. Afterwards the result is written back to main memory. Although the internal execution has several stages, no pipelining is present. This simplifies the control logic because no hazards can occur."
(из статьи "Designing and Manufacturing of Real Embedded Multi-Core CPUs: A Holistic Teaching Approach in Computer Architecture")
Надо прикинуть, сложно ли будет переделать его на 24-битный размер команды и 48-битное слово.
"The ZPU is a very small, 32-bit processor, advertised by the developer Zylin as “the worlds smallest 32-bit CPU with GCC toolchain” [14]. The hardware description is licensed under a FreeBSD license and the software under the GNU General Public License (GPL). Both license models offer free redistribution and adaption of the sources, which is a prerequisite for modifications of the design.
The architecture of one ZPU Core is shown in Figure 2. It consists of only three main components: 1. The control and execution unit Execute does the instruction execution and address calculation; 2. The instruction decoder Decode x4 which fetches up to four instructions for decoding; 3. The stack registers Stack A and Stack B where two words from the main memory (Memory) stack are temporarily stored. The ZPU is a stack-based architecture; apart from Stack A and Stack B the ZPU has no further registers. Every calculation is done by first fetching the appropriate words sequentially from the stack to the registers and then executing the instruction. Afterwards the result is written back to main memory. Although the internal execution has several stages, no pipelining is present. This simplifies the control logic because no hazards can occur."
(из статьи "Designing and Manufacturing of Real Embedded Multi-Core CPUs: A Holistic Teaching Approach in Computer Architecture")
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Date: 2019-02-04 17:19 (UTC)Что-то это мне напоминает!
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Date: 2019-02-04 18:44 (UTC)А у нас две - вся разница.
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Date: 2019-02-05 07:57 (UTC)